Showing posts with label Manipal University. Show all posts
Showing posts with label Manipal University. Show all posts

Tuesday, October 25, 2016

Manipal University admissions 2017 - Master of Engineering (ME) program at School of Information Sciences

 

 

Manipal University opens admissions for 2017 for Master of Engineering (ME) programs offered at School of Information Sciences, Manipal (SOIS)


                       Courses Offered:

                       ME (VLSI Design)

                       ME (Embedded Systems)

                       ME (Big Data & Data Analytics)

 


 

Eligibility:

 

Indian Nationals with a minimum of 50% aggregate in BE/BTech in Electronics & Communications, Computer Science, Information Science, Electrical & Electronics, Biomedical Engineering, Medical Electronics, Telecommunication Engineering or any other relevant branches of Engineering.


Admissions:

 

Admissions are done on the basis of marks obtained in the qualifying examination.


 

Last date to apply:                   30th November 2016

Commencement of Classes:   9th January 2017


For more details about the program and the institute, call 080-2925032 or email: office.sois@manipal.edu

 

Visit our website: www.manipal.edu/sois

 

 


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Wednesday, August 27, 2014

Attend a 2-day “Hands-on” Workshop on Digital Design using System Verilog - 19th & 20th Sep 2014


Workshop on Digital Design using System Verilog

 

19th and 20th September, 2014

Organized by

School of Information Sciences (SOIS)

Manipal University

 

Overview of the Workshop

 

The aim of this workshop is to give an overview and hands-on experience to the participants on the state-of-the-art tools for VLSI Design. This workshop comprises of theory along with the hands-on training on Digital Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification, Extraction, with hands-on session on System Verilog.

 

 

This course will be useful for the engineers who are interested to learn industry standard tool techniques of Analog & Digital IC Design

 

Who can attend?



Researchers, Academicians, UG & PG students, anyone.

 


Resource Persons

Academic Experts from Manipal University.

 

Important Dates:

Last date for registration : 10th-Sep-2014
Workshop date : 19th and 20th Sep, 2014

 

 

About SOIS:

School of Information Sciences (SOIS), a constituent institute of Manipal University, is an industry driven state-of-the-art training institute of excellence in the field of Medical Software, Embedded Systems and VLSI Design, set up in the year 1998


About VLSI Design Group: 

Since its inception, the group has been continuously striving for excellence in VLSI Design and training with a mission of offering value based education. The group is working in close association with industry giants like Synopsys Inc, NXPSemiconductors, WhizChip, Manipal Dot Net and a Consortium of other VLSI Design industries for its Post Graduate courses. The department is equipped with the cutting edge tools from Cadence, Xilinx, Altera, DSP boards etc.

Monday, August 11, 2014

Attend a 2-day “Hands-on” Workshop on Raspberry Pi using Python - 5th & 6th Sep 2014



Application development on Raspberry Pi using Python


Objective


The aim of this workshop is to give an overview of Python and Python Socket programming with an introduction to ARM Processor Architecture. It also includes introduction to Raspberry Pi board Architecture and compiling and porting of OS for Raspberry Pi. Thus providing a complete hands-on experience of application development on Raspberry Pi board using Python. 


Who can Attend

Researchers, Academicians, UG & PG students 
in the area of Electronics & Communication, 
Electrical & Electronics, Instrumentation & Control 
and other relevant streams of Engineering.

Resource Persons

Academic Experts from Manipal University.










About SOIS:

School of Information Sciences (SOIS), a constituent institute of Manipal University, is an industry driven state-of-the-art training institute of excellence in the field of Medical Software, Embedded Systems and VLSI Design, set up in the year 1998.


Saturday, August 9, 2014

Workshop on Analog and Digital IC Design using Cadence Tool - 6th Sep 2014


Workshop on VLSI Design using Cadence Design Suite

6th September, 2014

Organized by

School of Information Sciences (SOIS)

Manipal University


Overview of the Workshop



The aim of this workshop is to give an overview and hands-on experience to the participants on the state-of-the-art Cadence EDA tools for VLSI Design. This workshop comprises of theory along with the hands-on training on CMOS Analog and Digital Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), Extraction, with hands-on session on the Cadence design and simulation tools (NCSIM, RTLCompiler, Virtuoso, Spectre, etc.) and a real experience of using the standard cell design flow which is required for ASIC design.

This course will be useful for the engineers who are interested to learn industry standard tool techniques of Analog & Digital IC Design.

Who can attend?

Researchers, Academicians, UG & PG students in the area of Electronics & Communication, Electrical & Electronics, Instrumentation & Control and other relevant streams of Engineering.

Address for Correspondence:

The Workshop Coordinator,
SOIS, Lower Ground 2,
Academic Block 5, MIT Campus,
Manipal - 576104

Contact:

Madhushankara M, Assistant Professor,
Phone: 9449581104
workshop.sois@manipal.edu

Important Dates:


Last date for registration : 25th-Aug-2014
Workshop date : 06th-Sep-2014

Registration:

Fee: INR 1000

Maximum participants: 30 (FCFS basis)

The registration fee can be paid online or through a demand draft drawn in favour of Manipal University, payable at Manipal/Udupi.

For online payment:

Name    : Manipal University – Workshop
Address : Manipal University – Workshop,
                Finance Dept.
                Manipal University,
                Manipal - 576104

Designation  : Trust
Bank             : SBI
Branch          : Manipal
Branch Code : 04426

Account type & Number: SB #33508958510
                     IFSC Code: SBIN0004426
                    MICR Code: 576002006

About SOIS:

School of Information Sciences (SOIS), a constituent institute of Manipal University, is an industry driven state-of-the-art training institute of excellence in the field of Medical Software, Embedded Systems and VLSI Design, set up in the year 1998.

About VLSI Design Group:

Since its inception, the group has been continuously striving for excellence in VLSI Design and training with a mission of offering value based education. The group is working in close association with industry giants like Synopsys Inc, NXPSemiconductors, WhizChip, Manipal Dot Net and a Consortium of other VLSI Design industries for its Post Graduate courses. The department is equipped with the cutting edge tools from Cadence, Xilinx, Altera, DSP boards etc.


ITK VTK Workshop 2014

ITK VTK Workshop 6th Sep 2014, Manipal University


Medical Image Processing Workshop - 2014

Using Open Source Platform - ITK and VTK

6th Sep 2014

Organized by "School of Information Sciences"



Objective of this Workshop



To provide hands-on experience on Medical Image Processing application using an opensource platform Insight Toolkit (ITK) and Visualization Toolkit (VTK)






Focus :

  • Fundamentals of medical image processing
  • Insight Toolkit
  • Visualization Toolkit


Who can attend?


Researchers, Academicians, UG & PG students in the area of Biomedical Engineering, Medical Electronics, Medical Software, Computer Science, Electronics & Communication and other relevant streams.

Resource Persons:


Academic experts from Manipal University.

Registration:


Fee Rs. 1000
Maximum participants: 30
(First Come First Serve Basis)
Interested participants can register by sending an email to workshop.sois@manipal.edu

Venue:


SOIS, Lower Ground 2, Academic Block 5,
MIT Campus, Manipal,
Karnataka 576104

Contact:


Balaji B, Assistant Professor : 9964667208
Nandish S, Assistant Professor: 8105600172

Important Dates:


Last date for Registration : 25-08-2014
Workshop date : 06-09-2014

For online payment:


Name: Manipal University – Workshop
Address: Manipal University – Workshop,
Finance Dept. Manipal
University, Manipal - 576104
Bank: SBI Manipal
Account Number: 33508958510
IFSC Code: SBIN0004426




Sunday, September 29, 2013

Medical Image Processing Workshop using an open source platform - ITK and VTK (2013)

Medical Image Processing Workshop - 2013

Using Open Source Platform - ITK and VTK

25 and 26 Oct 2013

Organized by "School of Information Science"

and 

BoP, Manipal

Objective of this Workshop

ITK Insight Toolkit and VTK Visualization Toolkit

Workshop accompanied by eminent resource persons from Industry, Hospital and Academia

Venue: School of Information Science, Manipal

Last date for Registration - 18th Oct 2013

Limited Seats on First Come First Serve basis

For Details Contact: Mr. Balaji - 09964667208

Mr. Nandish - 08105600172


Saturday, February 4, 2012

Medical Image Processing Workshop using an open source platform - ITK and VTK


Objective: 
To provide hands on experience on Medical Image Processing applications using an open source platform - Insight Toolkit (ITK) & Visualization Toolkit (VTK)

Focus:
Participants will be given hands on experience and exposure to  
  • Fundamentals of Medical Image Processing
  • Visualization Toolkit (VTK)
  • Insight Toolkit (ITK)
  • Application development using ITK-VTK

Who can attend?
UG & PG Students in the area of Biomedical/Computer Science/Medical Software/Life Sciences/Allied Health Sciences and other interested streams.

Benefits to Participants
  • Participants get knowledge about application development for Medical Image Processing using open source platform (ITK & VTK)
  • Participants will be given certificates on successful completion of application development program.

     
Schedule:



  
 Maximum Participants - 25 (First Come First Serve Basis)
 Interested students can register at
 Manipal BoP Office, Academic Block 5, LG 02, MIT Campus, Manipal
 Ph. No: 0820-2925033


Last Date for Registration: February 10th 2012.

For more Details Contact:
Nandish S: 81056 00172 (Mob)

 

Thursday, January 19, 2012

4th - National Conference on Information Science, NCIS - 2012




&
Workshop
on
Signal Processing
23rd - 26th April, 2012

FPGA System Design using EDA Tools
25th - 26th April, 2012

Introduction
The Fourth National conference on Information Sciences (NCIS-2012) will be held during April  27th -28th, 2012 at Manipal Centre for Information Science (MCIS), Manipal, Karnataka, India. The institute is a state of the art of excellence, industry driven in the field of Health Care IT, VLSI, Embedded Systems, Wireless Technology.



MCIS was set up in the year 1998. The institute has been continuously striving for excellence in education and research with a mission of offering value based education. At MCIS, we create a vibrant atmosphere where the creativity and discipline strike balance. MCIS has been conducting Post Graduate courses in the highly specialized areas like Medical Software, VLSI Design, Embedded System Design, Mobile Computing, Virtualization, High Performance Computing and IT Management. All courses at MCIS has strong association with the industries like GE Medical Systems, Cerner, Synopsys, Philips, Whizchip, NXP Semiconductors, Manipal Dot Net and many more.

 Theme
NCIS provides the forum to researchers, engineers and academia to exchange the current and future trends in Healthcare IT, Electronics Sytsems Design and Information Sciences.

Conference Topics
  • Healthcare IT
  • VLSI Design
  • Embedded Systems
  • Mobile Computing
  • High Performance Computing
  • Virualization
  • Cloud Computing
Resource Persons
Eminent keynotes speakers from industries and R&D institutions will be invited to deliver special lectures on specific topics.

Participants
Academicians, engineers from industries, R&D personnel, researchers and industrialists from different parts of the country are invited to participate in the conference.

Call for Papers
One copy of the full paper not exceeding 6 pages, as per IEEE double column MS word format on any of the above related topics should be sent to the convener by e-mail. The accepted papers with full registration fees duly paid will be published in the proceedings of the conference; authors are requested to send their paper in editable format. PDF format will not be accepted.

Workshop - Signal Processing
The objective of the workshop is to give insight into bio-signal and speech processing.

Bio-Signal Processing: Introduction to signal processing, Concept of Bio signal processing, feature extraction, Dimensionality reduction, Statistics method LAB, Chi square test , ECG features, EEG signal processing, Basics of classifiers, NN, SVM, Signal processing using Speedy-33, NI kit.

Speech Signal Processing: A review Noise Estimation, Voice Activity detection Algorithm for ASR system, Speech Enhancement Algorithm for ASR system. Hybrid method for ASR system, Soft computing methods, Nonlinear models for Classifiers, Aggregation operators, SVD, K-means, EM, MRE, Chaos Theory.

DSP Architecture

Resource Person:
  • Dr Harikumar
  • Dr Ganesh Kumar
  • Engineer from Enixs
Workshop - FPGA System Design using EDA Tools
The main objective of the workshop is to turn the trainee into certified industry standard VLSI & Embedded System Design engineer. The training program consists of two primary modules. The first module focuses on latest trend in FPGA System Design, Quartus-2 version features, latest FPGA chips, Brushing up basics of Quartus-2 design flow, intro and implementation of state machine design entry, EDIF file, Integration to 3rd party EDA tools-Modelsim Functional and RTL level simulation, Debugging tools - Time quest analyzer tool, Power play power analyzer tool, Signal tap 2 embedded logic analyzer tool.

The second module gives and introduction to SOC and NOC based system designs and its latest trends, Brushing up SOPC based System Design, Interfacing Memory and its issues, Design of Embedded system design for real-time signal processing (Audio) and its verification, Intro and designing based on the next generation system integration tool from altera QSYS.


Resource Person:

  • Engineer from Enixs 

Maximum participation for the workshop is 30 numbers, it will be first come first serve basis. More about the workshop is attached and available at www.ncismanipal.org



The registration fee can be paid through a demand draft in favour of Manipal University, payable at Manipal/Udupi.


Downloads

Accommodation arrangements will be made on request.

For more information please visit







Chief Patron:
Dr Ramdas M Pai
Chancellor, Manipal University

Patron:
Dr H S Ballal
Pro-Chancellor, Manipal University
Dr Ramnarayan
Vice Chancellor, Manipal University
Dr H Vinod Bhat
Pro-Chancellor, Manipal University
Dr G K Prabhu
Registrar, Manipal University
Dr Kumkum Garg
Director, MIT, Manipal University

Chairman:
Prof Harishchandra Hebbar
Director, MCIS, Manipal University

Co-Chairman:
Prof Ramashesha C S
Prof Dinesh Rao
Prof Prashanth Kumar Shetty
Prof Arockiaraj S

Convenors:
Sundareshan C | Mohan Kumar J

Co-Convenors:
Balaji B | Chaitanya C V S

Coordinators:
Nandish S
Raghavendra Prabhu
Satyanarayan Shenoy P
Darryl Jeethesh D'Souza
Samarendranath Bhattacharya

Advisory Panel:
Dr N S Murthy, NXP Semiconductors, Bangalore
Dr Bhaskaran S, MaGE, Bangalore
Mr Balakrishna Rao, MaGE, Bangalore
Mr Ravishankar, Whizchip, Bangalore
Mr Vikas Soni, Whizchip, Bangalore
Dr Devi Prasad M, Robosoft, Udupi
Dr Shyam Vasudev, Forus, Bangalore
Mr Sayandeep Nag, Synopsys, Bangalore
Dr H G Joshi, MCIS, Manipal
Mr Shridhar Nayak, MCIS, Manipal
Mr Sathyendranath Malli, MCIS, Manipal
Mr Deepak Rao, MCIS, Manipal
Ms Keerthana Prasad, MCIS, Manipal
Ms Keerthana Balaji, MCIS, Manipal





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