Workshop on Digital Design using System Verilog
19th and 20th September, 2014
Organized by
School of Information Sciences (SOIS)
Manipal University
Overview of the Workshop
The aim of this workshop is to give an overview and hands-on experience to the participants on the state-of-the-art tools for VLSI Design. This workshop comprises of theory along with the hands-on training on Digital Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification, Extraction, with hands-on session on System Verilog.
This course will be useful for the engineers who are interested to learn industry standard tool techniques of Analog & Digital IC Design
Who can attend?
Researchers, Academicians, UG & PG students, anyone.
Resource Persons
Academic Experts from Manipal University.
Important Dates:
Last date for registration : 10th-Sep-2014
Workshop date : 19th and 20th Sep, 2014
Workshop date : 19th and 20th Sep, 2014